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NCP1910
OVP2
107% Vpref
+
?
“1” OVP2, “0” = ok
Latched adjustable OVP2
20 us filter
PFC_OVP2
latched
Grand Reset
PFC_BO
R
Q
Q
PFC_abnormal
latched
VOVP2
105% Vpref
VOVP
+
?
“1” OVP, “0” = ok
PFC_OVP
Auto ? recovery internal OVP
Vctrl(max)
PFCflag
1 sec
delay
+
S
FB
RFB
pull down
VUVP
8% Vpref
+
?
“1” = UVP, “0” ok
PFC_UVP
VDD
Vctrl
Vctrl(min) ? 0.1 V
Grand
Reset
PFC_BO
?
If PFC issues an abnormal
PFC_BO
Latch
Grand Reset
PFC_OPL
PFC_OK
IVLD
situation, then latch off
Dynamic
Response
Enhancer
“1” = below 5% reg
“0” ok
PFC_SKIP
(0.6 V clamp
voltage is
activated.)
R
S
Q
Q
PFC_OK
VLD
95% Vpref
Vctrl
Vfold
Vpref
Vfold(max)
OTA
“1” = FB > Vpref
Closed
if “1”
Ict(fold)
Grand Reset
PFC_BO
“1” open
“0” close
PFC drive signal
The “PFC_OK” toggles high when:
? VLD is low
? PFC issues a driving pulse
The “PFC_OK” toggles low when:
? Vctrl stays out of window [Vctrl,min to
Vctrl,max] > 1 sec
? at this point, the latch is reset and the
“PFC_OK” output goes low.
Grand Reset
PFC_BO
VCTRL
PFC_BO
LBO
VLBO
VLBOT
+
?
ILBO
“1” BO NOTOK,
“0” BOK
BO delay
Vctrl(min)
S
R
Q
Q
S
R
Q
Q
PFC_OK
VLBO^2
A
B
VDD Multiplier
Latch
Onoff
UVLO
TSD
PFC_SKIP
PFC_OL
PFC_OVP
PFC_BO
ICS
ICS
VLBO^2
Vpref
Vdd
CS
ICS
Vctrl ? Vctrl(min)
ICS VLBO2
4(Vctrl * Vctrl(min))
ICt(min)
ICt
ICS x VLBO^2
ICS x VLBO > 275 uA
+ “1” = OPL
?
PFC_OPL
Oscillator section
“0” / “1”
Vpref / 10%Vpref
VM
ICS > 200 uA
+
?
PFC_OL
“1” = OCP
PFC_OCP
Vcc
DRV
Figure 4. Internal PFC Block Diagram
http://onsemi.com
5
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